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5.5 Power Management
See the SATA specification for more information on SATA PHY power modes.
SATA PHY power modes affect only the SATA PHY, not the device power status. PHYSLP mode can be used by the
host to relatively quickly minimize (and restore) PHY power. It may also be used to further reduce CFast device
power after the host has sent commands to put the CFast device in a low power device state.
A device’s ability to support PHYSLP mode is indicated in Identify Drive Word 161 (CFast Specific Suppo rt).
5.5.1 PHYSLP protocol overview
If the host and device support PHYSLP mode the following protocols shall be used to enter and exit PHYSLP
mode.
To enter PHYSLP mode the protocol is:
a) The host shall send a request for the card to enter the SATA PHY Slumber mode. See the SATA
specification for more information.
b) After the CFast PHY has gone into Slumber power mode, the host shall deassert CDI.
c)
The host and the device shall power down their respective PHYs retaining calibration information.
d) After deasserting CDI and entering PHYSLP mode, the host may assert CDI for a period of less than one
millisecond to check for device presence.
To exit PHYSLP mode the protocol is:
a) The host shall assert CDI. The CFast card shall not respond to CDI assertions of less than two milliseconds.
b) The host and the device shall power up their respective PHYs into SATA PHY Slumber mode.
The device shall send a SATA COMWAKE signal to begin the SATA defined slumber to PHYRDY sequence (see section
“Power - On Sequence State Machine” in the SAT A specification).
Figure 4: PHYSLP entry timing diagram
Figure 5: PHYSLP exit timing diagram
Swissbit AG
Industriestrasse 4
Swissbit reserves the right to change products or specifications without notice.
Revision: 0.92
CH-9552 Bronschhofen
Switzerland
www.swissbit.com
industrial@swissbit.com
F-240_data_sheet_CA-HxBV_Rev092.doc
Page 13 of 56
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